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cyusb330x cyusb331x cyusb332x hx3 usb 3.0 hub cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? +1-408-943-2600 document number: 001-73643 rev. *f revised february 25, 2014 general description hx3 is a family of usb 3.0 hub controllers compliant with the us b 3.0 specification revision 1.0. hx3 supports superspeed (ss), hi-speed (hs), full-speed (fs), and low-speed (ls) on all the ports . it has integrated termination, pull-up, and pull-down resi stors, and supports configuration options through pin-stra ps to reduce the overall bom of the system. hx3 includes the following cy press-proprietary features: shared link?: enables extra downstream (ds) ports for on-board connections in embedded applications ghost charge?: enables charging of devices connecte d to the ds ports when no host is connected on the upstream (us) port hx3 usb 3.0 hub features usb 3.0-certified hub, tid# 330000047 supports up to four usb 3.0-compliant ds ports all ports support ss (5 gbps), and are backward-compatible with hs (480 mbps), fs (12 mbps), and ls (1.5 mbps) ss and usb 2.0 link power management (lpm) dedicated hi-speed transaction translators (multi-tt) led status indicators ? suspend, ss, and usb 2.0 operation shared link? for embedded applications each ds port can simultaneously connect to an embedded ss device and a removable usb 2.0 device enables up to eight device connections enhanced battery charging each ds port complies with the usb battery charging v1.2 (bc v1.2) specification ghost charge?: each ds port can emulate a dedicated charging port (dcp) when the host is not connected to the us port accessory charger adapter dock (aca-dock): enables charging and simultaneous data transfer for a smart phone or a tablet acting as a host compliant to bc v1.2 apple charging supported on all ds ports integrated arm ? cortex?-m0 cpu 16 kb ram, 32 kb rom configure gpios for overcurrent protection, power enable, and leds upgrade firmware using (a) i 2 c eeprom or (b) an external i 2 c master vendor-command support to implement a usb-to-i 2 c bridge firmware upgrade of an exte rnal assp connected to hx3 through usb in-system programming (isp) of the eeprom connected to hx3 through usb extensive configuration support pin-strap configuration for the following functions: ? vendor id (vid) ? charging support for each ds port ? number of active ports ? number of non-removable devices ? ganged or individual power switch enables for ds ports ? power switch polarity selection custom configuration modes supported with efuse, i 2 c eeprom, or i 2 c slave ? ss and usb 2.0 phy parameters ? product id (pid)/vid, manufacturer, and product string descriptors ? swap dp/dm signals for flexible pcb routing software features microsoft whql-certified for windows xp/vista/7/8/8.1 compatible with mac os 10.9 and linux kernel version 3.11 customize configuration para meters with the easy-to-use cypress?s ?blaster plus? software tool flexible packaging options 68-pin qfn (8 8 1.0 mm) 88-pin qfn (10 10 1.0 mm) industrial temperature range (?40 c to +85 c) errata: for information on silicon errata, see errata on page 30 . details include trigger conditions, devices affected, and proposed workaround. free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 2 of 33 block diagram usb 2.0 phy ss phy port control usb ? 2.0 ? phy ss phy vbus detect four transaction translators routing logic usb 2.0 ss repeater us port control routing buffer and routing logic hub controller phy interface ds buffers us buffers hub controller 3.3 v pll arm cortex-m0 ram rom 26 mhz 1.2 v usb 2.0 phy ss phy port control usb 2.0 phy ss phy port control usb 2.0 phy ss phy port control i2c i2c_data i2c_clk usb 2.0 controller ss controller us port dm ssrxp/m dp sstxp/m vbus led ovr pwr ds port 1 dm ssrxp/m dp sstxp/m led ovr pwr ds port 2 dm ssrxp/m dp sstxp/m led ovr pwr ds port 3 dm ssrxp/m dp sstxp/m led ovr pwr ds port 4 dm ssrxp/m dp sstxp/m free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 3 of 33 contents architecture overview 4 ss hub controller ....................................................... 4 usb 2.0 hub controller ............................................... 4 cpu ............................................................................. 4 i2c interface ................................................................ 4 port controller ............................................................. 4 applications ...................................................................... 4 product features .............................................................. 5 shared link ................................................................. 5 ghost charge .............................................................. 5 vendor-command support .... .............. .............. ......... 6 aca-dock support ...................................................... 6 pin information ................................................................. 7 system interfaces .... ............... ........... ........... ........... ....... 17 upstream port (us) ................................................... 17 downstream ports (ds1, 2, 3, 4) .............................. 17 communication interfaces (i2c ) ................................ 17 oscillator ............... .............. .............. .............. .......... 17 gpios ........................................................................ 17 power control ............................................................ 17 reset ......................................................................... 17 configuration mode select ..... .............. .............. ....... 17 configuration options ................................................ 17 emi ................................................................................... 24 esd .................................................................................. 24 absolute maximum ratings .......................................... 25 electrical specifications ................................................ 25 dc electrical characteristics ..................................... 25 power consumption .................................................. 26 ordering information ...................................................... 27 ordering code definitions ..... .................................... 27 package diagrams .......................................................... 28 acronyms ........................................................................ 29 reference documents .................................................... 29 document conventions ................................................. 29 units of measure ....................................................... 29 errata ............................................................................... 30 hx3 usb 3.0 hub qualification status ..................... 30 hx3 usb 3.0 hub errata summa ry .......................... 30 document history page ................................................. 32 sales, solutions, and legal information ...................... 33 worldwide sales and design s upport ......... .............. 33 products .................................................................... 33 psoc? solutions ...................................................... 33 cypress developer community ................................. 33 technical support ................. .................................... 33 free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 4 of 33 architecture overview the block diagram on page 2 shows the hx3 architecture. hx3 consists of two independent hub controllers (ss and usb 2.0), the cortex-m0 cpu subsystem, an i 2 c interface, and port controller blocks. ss hub controller this block supports the ss hub functionality based on the usb 3.0 specification. the ss hub controller supports the following: ss link power management (u0, u1, u2, u3 states) full-duplex data transmission usb 2.0 hub controller this block supports the ls, fs, and hs hub functionalities. it includes the repeater, frame time r, and four transaction trans- lators. the usb 2.0 hub controller block supports the following: usb 2.0 link power managemen t (l0, l1, l2, l3 states) suspend, resume, and remote wake-up signaling multi-tt (one tt for each ds port) cpu the arm cortex-m0 cpu subsystem is used for the following functions: system configuration and initialization battery charging control vendor-specific commands for the usb-to-i 2 c bridge string-descriptor support suspend status indicator shared link support in embedded systems i 2 c interface the i 2 c interface in hx3 supports the following: i 2 c slave, master, and multi-master configurations ? configure hx3 by an external i 2 c master in i 2 c slave mode ? configure hx3 from an i 2 c eeprom ? multi-master mode to share eeprom with other i 2 c masters in-system programming of the i 2 c eeprom from hx3?s us port port controller the port controller block controls ds port power to comply with the bc v1.2 and usb 3.0 specifications. this block also controls the us port power in the aca-dock mode. control signals for external power switches are implemented within the chip. hx3 controls the external power switches at power-on to reduce in-rush current. the port controller block supports the following: overcurrent detection ss and usb 2.0 port indicators for each ds port ganged and individual power control modes automatic port numbering based on active ports applications standalone hubs pc and tablet motherboards docking station hand-held cradles monitors digital tvs set-top boxes printers table 1. hx3 product options features cyusb3302 cyusb3304 cyusb3312 cyusb3314 CYUSB3326 cyusb3328 number of ds ports 2 (usb 3.0) 4 (usb 3.0) 2 (usb 3.0) 4 (usb 3.0) 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 8 (4 ss, 4 usb 2.0) number of shared link ports 000024 bc v1.2 yes yes yes yes yes yes aca-dock no no no no no yes external power switch control ganged ganged individual and ganged individual and ganged individual individual pin-strap support no no yes yes yes yes i 2 c yes yes yes yes yes yes vendor command yes yes yes yes yes yes port indicators no no yes yes no no packages 68-qfn 68-qfn 88-qfn 88-qfn 88-qfn 88-qfn temperature range industrial and commercial industrial and commercial industrial and commercial industrial and commercial industrial and commercial industrial and commercial free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 5 of 33 product features shared link figure 1. application of shared link in a notebook shared link is a cypress-proprie tary feature that enables a usb 3.0 port to be split into an embedded ss port and a standard usb 2.0 port. shared link enables a maximum of eight ds ports from a four-port usb 3.0 hub. for example, if one of the ds ports is connected to an embedded ss device, such as a usb 3.0 camera, hx3 enables the system designer to reuse the usb 2.0 si gnals of that specific port to connect to a standard usb 2.0 device. figure 1 shows how shared link can be used in an application. figure 2. ds port vbus control in shared link the shared link mode requires a separate vbus control for the usb 2.0 device and the embedded ss device. figure 2 shows the vbus control implementation. to ensure that the embedded ss device does not fall back to usb 2.0 operation, an external power switch is required. this switch is controlled by hx3, which generates an output signal called dsx_vbusen_sl. this sign al resets the vbus for the embedded device. dsx_pwren is another output signal generated by hx3 and controls vbus for the removable usb 2.0 device. for example, when an overcurrent condition occurs, dsx_pwren turns off the port power. ghost charge ghost charge is a cypress-proprietary feature for charging usb devices on the ds port when the us port is not connected to a host. for example, in a docking station with hx3 as shown in figure 3 , when the laptop is undocked, hx3 will emulate a dedicated charging port (dcp) to provide charge to a phone connected on a ds port. figure 3. ghost charge usb 3.0 example: shared link provide s six usb ports in a notebook d+ d- standard usb 2.0 port internal ss port sstx+ sstx- ssrx+ ssrx- usb 3.0 port split into ss port and standard usb 2.0 port usb 3.0 usb 2.0 wifi module ds4 pc chipset usb 3.0 host usb 2.0 ss (internal) usb 2.0 ss (internal) ds1 ds2 ds3 usb 3.0 camera us notebook pc motherboard hx3 hx3 4 2 6 usb 3.0 card reader 6 6 2 6 4 usb 3.0 port 6 usb 3.0 usb 3.0 superspeed phy usb 2.0 phy usb 3.0 ds port embedded superspeed device removable usb 2.0 device hx3 ssrxp/m sstxp/m dp dm vbus vbus dsx_vbusen_sl dsx_pwren charge a smartphone without do cking the notebook hx3 power to smartphone (hx3s downstream port) usb cable notebook pc undocked free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 6 of 33 when the us port is disconnect ed from the host, hx3 detects if any of the ds ports are connected to a device requesting charging. it determines the charging method and then switches to the appropriate signaling based on the detected charging specification as shown in figure 4 . the hub either emulates a usb-compliant dedicated charging port by connecting dp and dm (see the bc v1.2 specification) or other supported proprietary charging schemes. figure 4. ghost charge implementation in hx3 ghost charge is enabled by default and can be disabled through configuration. refer to configuration options on page 17 . vendor-command support hx3 supports vendor-specific r equests and can also enumerate as a vendor-specific device. the vendor-specific request can be used to (a) bridge usb and i 2 c and (b) configure hx3. this feature can be used for the following applications: firmware upgrade of an exte rnal assp connected to hx3 through usb in-system programming (isp) of an eeprom connected to hx3 through usb aca-dock support in traditional usb topologies, the host provides vbus to enable and charge the connected devices. for otg hosts, however, an aca-dock provides vbus and a method to charge the host. hx3 supports the aca-dock standard (see bc v1.2 specifi- cation) by integrating the func tions of the adapter controller. figure 5 shows the aca-dock system. if the aca-dock feature is enabled, hx3 turns on the external power switch to drive vbus on the us port. to inform that the otg host is connected to an aca-dock, the id pin is tied to ground using a resistor rid_a, as shown in figure 5 . the aca-dock feature can be disabled using the configuration options on page 17 . for example, a bc v1.2 compliant phone such as a sony xperia (neo v) can be docked to a hx3-based aca-dock system. the phone acts as an otg host and the aca-dock charges the phone connected to the us port while also powering the four ds ports. figure 5. aca-dock support wall charger detector other charging scheme bc v1.2 scheme charging scheme detector battery charger power switch dm 5 v dsx_pwren dsx_ovrcurr usb battery-powered device hx3 ds port dp vbus hx3 power switch vbus us_pwren vbus id to us otg enabled device pcb micro a plug vbus power source rid_a = 124 k ? free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 7 of 33 pin information figure 6. hx3 68-pin qfn 2-port pinout 1 gnd 68-pin qfn 68 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 67 19 20 66 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 30 56 55 31 54 32 33 53 52 34 2 vdd_efuse vbus_ds suspend reserved1 reserved2 mode_sel[0] mode_sel[1] nc rref_ss dvdd12 vdd_io pwr_en ovrcurr resetn i2c_clk i2c_data avdd12 nc dvdd12 ds2_txp ds2_txm dvdd12 ds2_rxm ds2_rxp avdd12 ds1_txp ds1_txm dvdd12 ds1_rxm ds1_rxp avdd12 avdd12 xtl_out xtl_in avdd33 us_dp us_dm ds1_dm ds1_dp avdd33 ds2_dp ds2_dm avdd33 dvdd12 rref_usb2 dvdd12 avdd33 us_txm us_txp dvdd12 us_rxm us_rxp avdd12 dvdd12 avdd12 vbus_us nc nc nc nc nc nc nc nc nc nc nc free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 8 of 33 figure 7. hx3 68-pin qfn 4-port pinout 1 gnd 68-pin qfn 68 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 67 19 20 66 65 21 64 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 30 56 55 31 54 32 33 53 52 34 2 vdd_efuse vbus_ds suspend reserved1 reserved2 mode_sel[0] mode_sel[1] nc rref_ss dvdd12 vdd_io pwr_en ovrcurr resetn i2c_clk i2c_data avdd12 ds3_rxp ds3_rxm dvdd12 ds3_txp ds3_txm ds2_txp ds2_txm dvdd12 ds2_rxm ds2_rxp avdd12 ds1_txp ds1_txm dvdd12 ds1_rxm ds1_rxp avdd12 avdd12 xtl_out xtl_in avdd33 us_dp us_dm ds1_dm ds1_dp avdd33 ds2_dp ds2_dm ds3_dm ds3_dp avdd33 ds4_dp ds4_dm dvdd12 rref_usb2 dvdd12 avdd33 us_txm us_txp dvdd12 us_rxm us_rxp avdd12 ds4_txp ds4_txm dvdd12 avdd12 ds4_rxm ds4_rxp vbus_us free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 9 of 33 table 2. 68-pin qfn pinout pin name type pin# description cyusb3302 cyusb3304 us port us_rxp i 9 superspeed receive plus us_rxm i 8 superspeed receive minus us_txp o 6 superspeed transmit plus us_txm o 5 superspeed transmit minus us_dp i/o 57 usb 2.0 data plus us_dm i/o 58 usb 2.0 data minus ds1 port ds1_rxp i 51 superspeed receive plus ds1_rxm i 50 superspeed receive minus ds1_txp o 47 superspeed transmit plus ds1_txm o 48 superspeed transmit minus ds1_dp i/o 60 usb 2.0 data plus ds1_dm i/o 59 usb 2.0 data minus ds2 port ds2_rxp i 45 superspeed receive plus ds2_rxm i 44 superspeed receive minus ds2_txp o 41 superspeed transmit plus ds2_txm o 42 superspeed transmit minus ds2_dp i/o 62 usb 2.0 data plus ds2_dm i/o 63 usb 2.0 data minus ds3 port nc ds3_rxp i 35 superspeed receive plus nc ds3_rxm i 36 superspeed receive minus nc ds3_txp o 38 superspeed transmit plus nc ds3_txm o 39 superspeed transmit minus nc ds3_dp i/o 65 usb 2.0 data plus nc ds3_dm i/o 64 usb 2.0 data minus ds4 port nc ds4_rxp i 15 superspeed receive plus nc ds4_rxm i 14 superspeed receive minus nc ds4_txp o 11 superspeed transmit plus nc ds4_txm o 12 superspeed transmit minus nc ds4_dp i/o 67 usb 2.0 data plus nc ds4_dm i/o 68 usb 2.0 data minus ovrcurr i 30 ganged overcurrent input pwr_en i/o 29 ganged power enable output nc i/o 25 nc free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 10 of 33 reserved1 i/o 21 this pin must be pulled high using a 10 k ? to vdd_io. reserved2 i 22 this pin must be pulled high using a 10 k ? to vdd_io. mode select, clock, and reset mode_sel[0] i 23 device operation mode select bi t 0; refer to ta b l e 4 mode_sel[1] i 24 device operation mode select bi t 1; refer to ta b l e 4 xtl_out a 54 crystal out xtl_in a 55 crystal in resetn i 31 active low reset input i2c_clk i/o 32 i 2 c clock i2c_data i/o 33 i 2 c data suspend i/o 20 hub suspend status indicator. this pin is asserted if both the ss and usb 2.0 hubs are in the suspend state and is de-asserted when either of the hubs comes out of the suspend state. power and ground vdd_efuse pwr 19 1.2 v normal operation, 2.5 v for programming avdd12 pwr 10, 16, 34, 46, 52, 53 1.2 v analog supply gnd pwr 40 gnd pin dvdd12 pwr 1, 3, 7, 13, 27, 37, 43, 49, 1.2 v core supply vbus _us pwr 17 this pin must be connected to vbus from us port vbus_ds pwr 18 this pin is used to power the apple-charging circuit in hx3. for bc v1.2 compliance testing, connec t pin to gnd. for normal operation, connect pin to local 5 v supply. avdd33 pwr 4, 56, 61, 66 3.3 v analog supply vdd_io pwr 28 3.3 v i/o supply usb precision resistors rref_usb2 a 2 connect pin to a precision resistor (6.04 k ?? 1%) to generate a current reference for usb 2.0 phy. rref_ss a 26 connect pin to a precision resistor (200 ? 1%) for ss phy termination impedance calibration. table 2. 68-pin qfn pinout (continued) pin name type pin# description cyusb3302 cyusb3304 free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 11 of 33 figure 8. hx3 88-pin qfn 2-port pinout 88-pin qfn 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 18 19 20 21 22 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 65 49 48 47 46 45 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 us_rxp us_rxm us_txp us_txm us_dp us_dm us_ovrcurr us_pwren ds1_rxp ds1_rxm ds1_txm ds1_txp ds1_dm ds1_dp ds2_dp ds2_dm ds2_rxp ds2_rxm ds2_txm ds2_txp nc ds1_ovrcurr ds1_pwren ds1_amber ds1_green ds1_led_ss ds2_amber ds2_green ds2_ovrcurr ds2_pwren ds2_led_ss ds3_pwren ds3_amber ds3_ovrcurr ds3_green ds3_led_ss ds4_ovrcurr ds4_pwren/pwr_en4 ds4_amber ds4_green ds4_led_ss i2c_clk i2c_data resetn vdd_io dvdd12 rref_ss avdd12 vdd_efuse vbus_ds suspend reserved1 mode_sel[0] mode_sel[1] dvdd12 avdd12 gnd dvdd12 dvdd12 avdd12 avdd12 vdd_io avdd33 avdd33 avdd33 dvdd12 vdd_io rref_usb2 dvdd12 avdd33 dvdd12 avdd12 dvdd12 avdd12 vbus_us xtl_in xtl_out nc nc nc nc nc nc nc nc nc nc nc free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 12 of 33 figure 9. hx3 88-pin qfn 4-port pinout 88-pin qfn 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 2 18 19 20 21 22 66 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 65 49 48 47 46 45 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 us_rxp us_rxm us_txp us_txm us_dp us_dm us_ovrcurr us_pwren ds1_rxp ds1_rxm ds1_txm ds1_txp ds1_dm ds1_dp ds2_dp ds2_dm ds3_dm ds3_dp ds4_dp ds4_dm ds2_rxp ds2_rxm ds2_txm ds2_txp ds3_txm ds3_txp ds3_rxm ds3_rxp ds4_txp ds4_txm ds4_rxm ds4_rxp ds1_ovrcurr ds1_pwren ds1_amber ds1_green ds1_led_ss ds2_amber ds2_green ds2_ovrcurr ds2_pwren ds2_led_ss ds3_pwren ds3_amber ds3_ovrcurr ds3_green ds3_led_ss ds4_ovrcurr ds4_pwren/pwr_en4 ds4_amber ds4_green ds4_led_ss i2c_clk i2c_data resetn vdd_io dvdd12 rref_ss avdd12 vdd_efuse vbus_ds suspend reserved1 mode_sel[0] mode_sel[1] dvdd12 avdd12 gnd dvdd12 dvdd12 avdd12 avdd12 vdd_io avdd33 avdd33 avdd33 dvdd12 vdd_io rref_usb2 dvdd12 avdd33 dvdd12 avdd12 dvdd12 avdd12 vbus_us xtl_in xtl_out free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 13 of 33 table 3. 88-pin qfn pinout pin name type pin# description cyusb3312 cyusb3314 CYUSB3326 cyusb3328 us port us_rxp i 14 superspeed receive plus us_rxm i 13 superspeed receive minus us_txp o 11 superspeed transmit plus us_txm o 10 superspeed transmit minus us_dp i/o 71 usb 2.0 data plus us_dm i/o 72 usb 2.0 data minus us_ovrcurr i 39 cyusb3328: overcurrent detect input for us port in aca-dock mode. if aca-dock mode is disabled using configuration options on page 17 , this pin must be pulled high using a 10 k ? to vdd_io. other part numbers: this pin must be pulled high using a 10 k ? to vdd_io. us_pwren [1] i/o 31 cyusb3328: vbus power enable output for us port in aca-dock mode. if aca-dock mode is disabled using configuration options on page 17 , this pin can be left floating if pin-strap is not enabled. other part numbers: this pin can be left floating if pin-strap (pin# 63) is not enabled. pwr_sw_pol [2] this pin is called pwr_sw_pol in pin-strap configuration mode. ds1 port ds1_rxp i 61 superspeed receive plus ds1_rxm i 60 superspeed receive minus ds1_txp o 57 superspeed transmit plus ds1_txm o 58 superspeed transmit minus ds1_dp i/o 74 usb 2.0 data plus ds1_dm i/o 73 usb 2.0 data minus ds1_ovrcurr i 42 overcurrent detect input for ds1 port ds1_pwren [1] i/o 38 vbus power enable output for ds1 port. when t he port is disabled, this pin is in tristate. ds1_cdp_en [2] this pin is called ds1_cdp_en in pin-strap configuration mode. ds1_amber [1] i/o 2 led_amber output for ds1 port aca_dock [2] this pin is called aca-dock in pin-strap configuration mode. ds1_green [1] i/o 3 cyusb3312/3314: led_green output for ds1 port ds1_vbusen_sl [1] CYUSB3326/3328: vbus power enable output for ss port 1 port_disable[0] [2] this pin is called port_disable[0] in pin-strap configuration mode. ds1_led_ss [1] i/o 4 led_ss output for ds1 port port_disable[1] [2] this pin is called port_disable[1] in pin-strap configuration mode. notes 1. this pin can be configured as a gpio usi ng custom firmware. for information contact www.cypress.com/support . 2. for pin-strap configuration details, refer to ta b l e 5 . free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 14 of 33 ds2 port ds2_rxp i 55 superspeed receive plus ds2_rxm i 54 superspeed receive minus ds2_txp o 51 superspeed transmit plus ds2_txm o 52 superspeed transmit minus ds2_dp i/o 76 usb 2.0 data plus ds2_dm i/o 77 usb 2.0 data minus ds2_ovrcurr i 1 overcurrent detect input for ds2 port ds2_pwren [3] i/o 86 vbus power enable output for ds2 port. when t he port is disabled, this pin is in tristate. ds2_cdp_en [4] this pin is called ds2_cdp_en in the pin-strap configuration mode. ds2_amber [3] i/o 5 led_amber output for ds2 port non_removable[0] [4] this pin is called non_removable[0] in the pin-strap configuration mode. ds2_green [3] i/o 6 cyusb3312/3314: led_green output for ds2 port ds2_vbusen_sl [3] CYUSB3326/3328: vbus power enable output for ss port 2 non_removable[1] [4] this pin is called non_removable[1] in the pin-strap configuration mode. ds2_led_ss [3] i/o 84 led_ss output for ds2 port pwr_en_sel [4] this pin is called pwr_en_sel in the pin-strap configuration mode. ds3 port nc ds3_rxp i 45 superspeed receive plus nc ds3_rxm i 46 superspeed receive minus nc ds3_txp o 48 superspeed transmit plus nc ds3_txm o 49 superspeed transmit minus nc ds3_dp i/o 79 usb 2.0 data plus nc ds3_dm i/o 78 usb 2.0 data minus ds3_ovrcurr i 65 cyusb3314/3326/3328: overcurr ent detect input for ds3 port cyusb3312: this pin must be pulled high using a 10 k ? to vdd_io. ds3_pwren [3] i/o 87 vbus power enable output for ds3 port. when t he port is disabled, this pin is in tristate. ds3_cdp_en [4] this pin is called ds3_cdp_en in the pin-strap configuration mode. ds3_amber [3] i/o 85 led_amber output for ds3 port vid_sel[2] [4] this pin is called vid_sel[2] in the pin-strap configuration mode. table 3. 88-pin qfn pinout (continued) pin name type pin# description cyusb3312 cyusb3314 CYUSB3326 cyusb3328 notes 3. this pin can be configured as a gpio usi ng custom firmware. for information contact www.cypress.com/support . 4. for pin-strap configuration details, refer to ta b l e 5 . free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 15 of 33 ds3_green [5] i/o 64 cyusb3312/3314: led_green output for ds3 port ds3_vbusen_sl [5] CYUSB3326/3328: vbus power enable output for ss port 3 vid_sel[1] [6] this pin is called vid_sel[1] in the pin-strap configuration mode. for pin-strap configuration details, refer to ta b l e 5 . ds3_led_ss [5] i/o 63 led_ss output for ds3 port pin_strap [6] this pin is called pin_strap in pin-st rap configuration mode. when connected to vdd_io through a 10-k ? resistor, this pin enables pin-strap configuration mode for hx3. ds4 port nc ds4_rxp i 20 superspeed receive plus nc ds4_rxm i 19 superspeed receive minus nc ds4_txp o 16 superspeed transmit plus nc ds4_txm o 17 superspeed transmit minus nc ds4_dp i/o 81 usb 2.0 data plus nc ds4_dm i/o 82 usb 2.0 data minus ds4_ovrcurr i 36 cyusb3314/3326/3328: overcurrent detect input for ds4 port. cyusb3312: this pin must be pulled high using a 10 k ? to vdd_io. ds4_pwren/pwr_en4 i/o 35 vbus power enable output for ds4 port. this pin is also used as power enable output when configured in ganged power mode using the blaster plus tool. when the port is disabled, this pin is in tristate. ds4_cdp_en [6] this pin is called ds4_cdp_en in the pin-strap configuration mode. ds4_amber [5] i/o 30 led_amber output for ds4 port i2c_dev_id [6] this pin is called i2c_dev_id in the pin-strap configuration mode. ds4_green [5] i/o 43 cyusb3312/3314: led_green output for ds4 port ds4_vbusen_sl CYUSB3326/3328: vbus power enable output for ss port 4 vid_sel[0] [6] this pin is called vid_sel[0] in the pin-strap configuration mode. ds4_led_ss i/o 26 led_ss output for ds4 port. the led must be connected to gnd as shown in figure 12 on page 18 . if led is not used, this pin must be pulled high using a 10 k ? to vdd_io. reserved1 i 27 this pin must be pulled high using a 10 k ? to vdd_io. mode select, clock, and reset mode_sel[0] i 28 device operation mode select bit 0; refer to table 4 mode_sel[1] i 29 device operation mode select bit 1; refer to table 4 xtl_out a 68 crystal out xtl_in a 69 crystal in resetn i 37 active low reset input i2c_clk i/o 40 i 2 c clock i2c_data i/o 41 i 2 c data table 3. 88-pin qfn pinout (continued) pin name type pin# description cyusb3312 cyusb3314 CYUSB3326 cyusb3328 notes 5. this pin can be configured as a gpio usi ng custom firmware. for information contact www.cypress.com/support . 6. for pin-strap configuration details, refer to ta b l e 5 . free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 16 of 33 suspend i/o 25 hub suspend status indicator. this pin is asserted if both the ss and usb 2.0 hubs are in the suspend state and is de -asserted when either of the hubs comes out of the suspend state. power and ground vdd_efuse pwr 24 1.2 v normal operation, 2.5 v for programming avdd12 pwr 15, 21, 44, 56, 62, 67 1.2 v analog supply gnd pwr 50 gnd pin dvdd12 pwr 8, 12, 18, 33, 47, 53, 59, 83 1.2 v core supply vbus _us pwr 22 cyusb3328: connect the vbus_us pin to the local 5 v supply. if aca-dock mode is disabled using configuration options on page 17 , this pin must be connected to vbus from us port. other part numbers: this pin must be connected to vbus from us port. vbus_ds pwr 23 this pin is used to power the apple-charging circuit in hx3. for bc v1.2 compliance testing, conne ct pin to gnd. for normal operation, connect pin to local 5 v supply. avdd33 pwr 9, 70, 75, 80 3.3 v analog supply vdd_io pwr 34, 66, 88 3.3 v i/o supply usb precision resistors rref_usb2 a 7 connect pin to a precision resistor (6.04 k ? 1%) to generate a current reference for usb 2.0 phy. rref_ss a 32 connect pin to a precision resistor (200 ? 1%) for ss phy termination impedance calibration. table 3. 88-pin qfn pinout (continued) pin name type pin# description cyusb3312 cyusb3314 CYUSB3326 cyusb3328 free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 17 of 33 system interfaces upstream port (us) this port is compliant with the usb 3.0 specification and includes an integrated 1.5 k ? pull-up and termination resistors. it also supports aca-dock to enable charging an otg host connected on the us port. downstream ports (ds1, 2, 3, 4) ds ports are compliant with the usb 3.0 specification and integrate 15 k ? pull-down and termination resistors. ports can be disabled or enabled, and can be set to removable or non-removable options. bc v1.2 charging is enabled by default and can be disabled on each ds port using the configuration options (see configuration options ). communication interfaces (i 2 c) the interface follows the inter-ic bus specification, version 3.0, with support for the standard mode (100 khz) and the fast mode (400 khz) frequencies. hx3 supports i 2 c in the slave and master modes. the i 2 c interface supports the multi-master mode of operation. both the scl and sda signals require external pull-up resistors based on the specification. vdd_io for hx3 is 3.3 v and it is expected that the i 2 c pull-up resistors will be connected to the same supply. oscillator hx3 requires an external crystal with a frequency of 26 mhz and an accuracy of 150 ppm in parallel resonant, fundamental mode. the crystal drive circuit is capable of a low-power drive level (<200 w). the crystal connection to the xtl_out and xtl_in pins is shown in figure 10 . figure 10. crystal connection gpios hx3 gpios are used for overcu rrent sensing, controlling external power switches, and driving leds. these pins can sink up to 4 ma current each. gpios also enable pin-straps for input configuration. refer to table 5 for more details. power control the pwr_en[1-4] and ov_curr[1-4] pins interface hx3 to external power switches. these pins are used to control power switches for ds port power and monitor overcurrent conditions. the power switch polarity and the power control mode (individual and ganged) can be changed using the configuration options. reset hx3 operates with two external power supplies, 3.3 v and 1.2 v. there is no power sequencing requirement between these two supplies. however, the reset n pin should be held low until both these supplies become stable. the resetn pin can be tied to vdd_io through an external resistor and to ground (gnd) through an external capacitor (minimum 5 ms time cons tant), as shown in figure 11 . this creates a clean reset signal for power-on reset (por). hx3 does not support internal br own-out detection. if the system requires this feature, an external reset should be provided on the resetn pin when supplies are below their valid operating ranges. figure 11. reset connection configuration mode select configuration options are selected through the mode_sel pins and the pin-strap enable pin (pin_strap). after power-up, these pins are sampled by an on-chip bootloader to determine the configuration options (see ta b l e 4 ). configuration options hx3 can be configured by using one of the following: efuse (one-time programmable memory) pin-strap (read configuration fr om dedicated pins at power on) external i 2 c slave such as an eeprom external i 2 c master the i 2 c master/slave configuration overrides the pin-strap configuration. pin-straps overri de the efuse configuration, and the efuse configuration overrides the internal rom configuration. efuse configuration hx3 contains efuses, which are otp elements on the chip that can be electrically blown. the efuses are read by the bootloader to determine the customer-specific configurations. efuse programming is supported only at factory and distributor locations where programming conditions can be controlled. 10 pf 10 pf 26 mhz xtl_out xtl_in table 4. hx3 boot sequence mode sel[1] mode sel[0] hx3 configuration modes 0 0 reserved. do not use this mode. 1 1 internal rom configuration (see errata on page 30 ) 01i 2 c master, read configuration from i 2 c eeprom * 10i 2 c slave, configure from an external i 2 c master * * download cypress-provided firmware from www.cypress.com/hx3. resetn vdd_io 1.5 f 10 k ? free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 18 of 33 efuse programming is supported under the following conditions: temperature range of 25 c?70 c and programming voltage of 2.5 v?2.7 v. pin-strap configuration pin-straps are supported for select product options (see table 1 ) to provide reconfigurability without an additional eeprom. the pin-strap configuration is enabled by pulling the pin #63 of 88-pin qfn high. table 5 shows the configuration options supported through pin-straps and the gpios used for this purpose. figure 12 and figure 13 show how the gpios need to be connected if pin-strap and led connection are required or only pin-strap is required. hx3 samples pin-strap gpios at power-up. floating straps are considered as invalid and the def ault configuration is used. if pin_strap (pin #63 of 88-pin qfn) is floating, all strap inputs are considered invalid. a gpio is considered strapped ?1? or ?0? when connected with a weak pull-up (10 k ? ) or pull-down (10 k ? ) respectively. after the initial sampling at power-up and reset, the gpios are used in their normal functions. figure 12. pin-strap with led or led-only connection figure 13. pin-strap connection vdd_io to gpio 800 ? ? 1 k ? 800 ? ? 1 k ? vss to gpio 10 k ? 10 k ? pin-strap high with led pin-strap low with led to gpio vdd_io 10 k ? 10 k ? to gpio vss pin-strap high pin-strap low notes 7. see figure 12 and figure 13 . 8. dsx_cdp_en will be active low input when pwr_sw_pol is set to active low; similarly dsx_cdp_en will be active high input when pwr_sw_pol is set to active high. 9. these ds ports are exposed ports and the connected devices can be removed. 10. vid, port_disable, non_removable are group straps. if one of the pins in a group strap is floating (invalid), that group inp ut will be invalid and the default will not be overwritten. 11. i2c_dev_id is valid only when hx3 is in i 2 c slave mode. table 5. pin-strap configuration 88-qfn pin # pin-strap name strapped ?0? [7] strapped ?1? [7] 31 pwr_sw_pol power enable and overcurrent will be active low power enable and overcurrent will be active high strapped ?0? strapped ?1? strapped ?0? strapped ?1? 38 ds1_cdp_en [8] ds1 cdp enabled ds1 cdp disabled ds1 cdp disabled ds1 cdp enabled 86 ds2_cdp_en [8] ds2 cdp enabled ds2 cdp disabled ds2 cdp disabled ds2 cdp enabled 87 ds3_cdp_en [8] ds3 cdp enabled ds3 cdp disabled ds3 cdp disabled ds3 cdp enabled 35 ds4_cdp_en [8] ds4 cdp enabled ds4 cdp disabled ds4 cdp disabled ds4 cdp enabled 2 aca_dock disabled enabled 4 port_disable[1] port_disable[1:0] = b?00: ds1, ds2, ds3, ds4 active b?01: ds1, ds2, ds3 active b?10: ds1, ds2 active b?11: ds1 active pin-straps cannot enable ports disabled by factory setting. 3 port_disable[0] 6 non_removable[1] [9] non_removable[1:0] = b?00: ds1, ds2, ds3, ds4 removable b?01: ds1, ds2, ds3 removable b?10: ds1, ds2 removable b?11: ds1 removable 5 non_removable[0] [9] 84 pwr_en_sel individual gang 85 vid[2] reserved. if pin_strap is enabled and cy vid is required, strap vid[2:0] to ?1?. 64 vid[1] 43 vid[0] 63 pin_strap [10] no pin-strapping pin-strapping configuration enabled 30 i2c_dev_id [11] id 0: hx3 i 2 c slave address (7 bits) is 0x60. this is also the default i 2 c slave address for the 68-pin qfn package. id 1: hx3 i 2 c slave address (7 bits) is 0x58 free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 19 of 33 i 2 c configuration when enabled for i 2 c configuration through the mode_sel pins (see ta b l e 4 ), hx3 can be configured as an i 2 c master or as an i 2 c slave. hx3?s configuration data is a maximum of 197 bytes and hx3?s firmware is 10 kb. note that hx3?s firmware also includes configuration settings. hx3 as i 2 c master hx3 reads configurations from an external i 2 c eeprom with sizes ranging from 16 to 64 kb. an example of a supported eeprom is 24lc128. based on the contents of the bsignature and bimagetype fields in ta b l e 6 , hx3 performs one of the following actions: loads custom configuration settings from the eeprom when bsignature is ?cy? and bimagetype is 0xd4. loads the cypress-provided firmware from the eeprom when bsignature is ?cy? and bimagetype is 0xb0. this firmware also includes configuration settings. if bsignature ? ?cy?, hx3 enumerates in the vendor-specific mode. the contents of the eeprom can be updated with the easy-to-use cypress blaster plus tool. blaster plus is a gui-based tool to configure hx3. this tool allows to do the following: download the cypress-provided firmware from a pc via hx3's us port and store it on an eeprom connected to hx3?s i 2 c port. read the configuration sett ings from the eeprom. these settings are displayed in the blaster plus gui. modify settings as required. write back the updated settings on to the eeprom. in addition, an image file can be created for external use. the blaster plus tool, user guide, and the cypress-provided firmware are available at www.cypress.com/hx3 . hx3 as i 2 c slave an external i 2 c master can program the configuration settings into hx3 according to the eeprom map in table 6 . alternatively, the hx3 firmware (<10 kb), which includes configuration settings, can also be programmed. it is recommended to use the blaster plus tool to create the hx3 firmware or configuration image file. hx3?s i 2 c slave address needs to be provided while creating the image file. refer to ta b l e 5 for hx3?s i 2 c slave address. table 6. eeprom map i 2 c offset bits name default description 0 7:0 bsignature lsb (?c?) 0x43 two-byte signature initialized with ?cy? ascii text when the signature is not valid, the hub enumerates as a vendor-specific device. 1 7:0 bsignature msb (?y?) 0x59 two-byte signature initialized with ?cy? ascii text when the signature is not valid, the hub enumerates as a vendor-specific device. 2 7:6 bimagectl b?00 reserved 5:4 i 2 c speed b?11 b?01: 400 khz b?11: 100 khz 3:1 bimagectl b?000 reserved 0 bimagectl 0 0: execution binary file 1: data file 3 7:0 bimagetype 0xd4 0xd4: load only configuration 0xb0: load firmware boot image all other bimagetype will return an error code. 4 7:0 bd4length 192 bd4length is defined in bytes as the length from offset 5. i 2 c offset bytes 0?4 are the header bytes. bd4length = 6: only upda te vid, pid, and did bd4length = 18: configuration options (no phy trim) bd4length = 40: configuration options with phy trim options bd4length > 40: user must provide valid string descriptors bd4length > 192: error 5 7:0 vid [7:0] 0xb4 custom vendor id - lsb 6 7:0 vid [15:8] 0x04 custom vendor id - msb 7 7:0 pid [7:0] 0x04 custom product id (pid) default: 0x6504 if separate pid is used for u sb 2.0, the usb 2.0 pid will be read from offset 35 and 36. else, usb 2.0 pid = 0x6506 8 7:0 pid [15:8] 0x65 free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 20 of 33 9 7:0 did [7:0] 0x00 - 88-pin qfn, 0x10 - 68-pin qfn custom device id - revision 10 7:0 did [15:8] 0x50 custom device id - revision 11 7:0 reserved 0 reserved 12 7:4 shared_link_en b?0000 enable shared link bit[7:4]=ds4, ds3, ds2, ds1 0: not active 1: active 3:0 shc_active_ports [3:0] b?1111 indicates if a superspeed port is active. bit[3:0] = ds4, ds3, ds2, ds1 0: not active 1: active 13 7:0 power_on_time 0x32 time (in 2-ms intervals) from the time the power-on sequence begins on a port until power is good on that port (bpwron2pwrgood) 14 7:4 removable_ports [3:0] b?1111 indic ates if the port is removable. bit[7:4]=ds4, ds3, ds2, ds1 0: non-removable 1: removable 3:0 uhc_active_ports [3:0] b?1111 indic ates if a usb 2.0 port is active. bit[3:0]=ds4, ds3, ds2, ds1 0: not active 1: active 15 7 ss_led_pin_control 0 port 1?4: ss led disable 0: ds[1:4]_led_ss are leds. the led glows when the ss port is active and not in disabled state. 1: ds[1:4]_led_ ss are not leds 6 green_led_pin_control 0 port 1? 4: usb 2.0 green led disable 0: ds[1:4]_green are leds 1: ds[1:4]_green are not leds 5 amber_led_pin_control 0 port 1?4: usb 2.0 amber led disable 0: ds[1:4]_amber are leds 1: ds[1:4]_amber are not leds 4 port_indicators 1 port indicators supported 0: port indicators are not suppor ted on its ds-facing ports and the usb 2.0 port_indicator request has no effect. 1: port indicators are supported on its ds-facing ports and the usb 2.0 port_indicator request controls the indicators. 3 compound_hub 0 identifies a compound device. 0: hub is not part of a compound device. 1: hub is part of a compound device. 2:1 reserved 0 reserved 0 gang 0 1: ganged power switch enable for all ds ports 0: individual port power switch enable for each ds port table 6. eeprom map (continued) i 2 c offset bits name default description free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 21 of 33 16 7 suspend_indicator_disabl e 0 0: suspend indicator enabled 1: suspend indicator disabled 6 ss_us_disable 0 hub mode of op eration (usb 3.0 or usb 2.0) 0: usb 3.0 hub and usb 2.0 hub enabled 1: usb 3.0 hub disabled and usb 2.0 hub enabled 5 pwr_en_polarity 0 power control output polarity 0: active low 1: active high 4:0 port_polarity b?00000 usb 2.0 dp and dm swapped bit[4:0]=ds4, ds3, ds2, ds1, us 1: port polarity swapped 0: port polarity not swapped 17 7:5 reserved 0 reserved 4 bc_enable 1 0: bc v1.2 disabled 1: bc v1.2 enabled 3 aca_dock 0 if this bit is set, enable aca-dock on the us port 2 apple_xa 0 0: max limit for apple charging 2.1 a 1: max limit for apple charging 1 a 1 reserved 0 reserved 0 ghost_charge_en 1 0: ghost charging disabled 1: ghost charging enabled 18 7:4 cdp_en[3:0] b?1111 per-port charging setting bit[7:4]=ds4, ds3, ds2, ds1 0: cdp disabled 1: cdp enabled 3:0 dcp_en[3:0] b?0000 per-port charging setting bit[3:0]=ds4, ds3, ds2, ds1 0: dcp disabled 1: dcp enabled 19 7 embedded_hub 0 if this bit is set, the us is as an embedded port and vbus connected to vbus_us pin is ignored. 6 illegal_descriptor 1 if this bit is set, the u sb 2.0 hub controller wil l accept both 0x00 and 0x29 as valid descriptor types. if '0', only 0x29 will be accepted as a valid descriptor type. 5 modulate_indicator 1 if this bit is set, the led outputs will be modulated by a 200 hz square wave for power saving. if ?0?, the outputs will be static. 4 oc_polarity 0 overcurrent input polarity 0: active low 1: active high 3:0 oc_timer b?1000 time in milliseconds for wh ich the overcurrent inputs will be filtered 20 7:0 reserved 0 reserved 21 7:4 reserved 0 reserved 3 string_descriptor_enable 0 0: string descriptor support is disabled 1: string descriptor support is enabled when string descriptors are not supported, the hub controller returns a non-zero index (compile-time programmable) for each string which is supported, and 0x00 for each string not supported, as indicated by this field. 2:0 reserved 0 reserved 22 7:0 reserved 0 reserved table 6. eeprom map (continued) i 2 c offset bits name default description free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 22 of 33 23 7:6 hs_amplitude_ds4 b?00 hs driver amplitude control; hs driver cu rrent: +0% to +7.5% b?00: default b?01: +2.5% b?10: +5% b?11: +7.5% 5:4 hs_amplitude_ds3 b?00 3:2 hs_amplitude_ds2 b?00 1:0 hs_amplitude_ds2 b?00 24 7:6 hs_amplitude_us b?00 5:2 hs_slope b'0100 hs driver slope control for all ports b?0000: +15% b?0001: +5% b?0100: default b?0101: -5% b?1111: -7.5% 1:0 hs_tx_vref b?10 reference voltage for hs squelch (transmission envelope detector) for all ports b?00: 96 mv b?01: 108 mv b?10: 120 mv b?11: 132 mv 25 7:3 hs_preemp_en[4:0] b?00000 hs dr iver pre-emphasis enable ? for por ts ds4, ds3, ds2, ds1, and us 0: pre-emphasis is disabled 1: pre-emphasis is enabled 2 hs_preemp_depth_ds4 [12] 0 hs driver pre-emphasis depth 0: +10% 1: +20% 1 hs_preemp_depth_ds3 [12] 0 0 hs_preemp_depth_ds2 [12] 0 26 7 hs_preemp_depth_ds1 [12] 0 6 hs_preemp_depth_us [12] 0 5 reserved 1 reserved 4:1 pcs_tx_deemph_ds4 0x6 usb 3.0 tx driver de-emphasis value 0x3: -2.75 db 0x6: -3.4 db (default) 0x9: -4.0 db 0 reserved 0 reserved 27 7:4 pcs_tx_deemph_ds3 0x6 usb 3.0 tx driver de-emphasis value 0x3: -2.75 db 0x6: -3.4 db (default) 0x9: -4.0 db 3:0 pcs_tx_deemph_ds2 0x6 28 7:4 pcs_tx_deemph_ds1 0x6 3:0 pcs_tx_deemph_us 0x6 29 7 reserved 0 reserved 6 reserved 1 reserved 5:0 pcs_tx_swing_full_ds4 0x29 adjust launch amplitude of the transmitter 0x1f ? 0.9 v 0x29 ? 1.0 v (default) 0x35 ? 1.1 v 0x3f ? 1.2 v 30 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds3 0x29 adjust launch amplitude of the transmitter 0x1f ? 0.9 v 0x29 ? 1.0 v (default) 0x35 ? 1.1 v 0x3f ? 1.2 v table 6. eeprom map (continued) i 2 c offset bits name default description note 12. hs_preemp_depth is valid only when corresponding hs_preemp_en is set for that port. free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 23 of 33 31 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds2 0x29 adjust launch amplitude of the transmitter 0x1f ? 0.9 v 0x29 ? 1.0 v (default) 0x35 ? 1.1 v 0x3f ? 1.2 v 32 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_ds1 0x29 adjust launch amplitude of the transmitter 0x1f ? 0.9 v 0x29 ? 1.0 v (default) 0x35 ? 1.1 v 0x3f ? 1.2 v 33 7:6 reserved 0 reserved 5:0 pcs_tx_swing_full_us 0x29 adjust la unch amplitude of the transmitter 0x1f ? 0.9 v 0x29 ? 1.0 v (default) 0x35 ? 1.1 v 0x3f ? 1.2 v 34 7:0 reserved 0 reserved 35 7:0 uhc_pid [7:0]_lsb 0x0 6 usb 2.0 pid. if bd4length ? 40, usb 2.0 pid will be read from this location. 36 7:0 uhc_pid [15:8]_msb 0x65 37?44 7:0 reserved 0 eight bytes reserved for future expansion 45 7:0 blength: langid 4 size of l angid (defined by spec as n+2) 46 7:0 desctype 3 string descriptor type (constant value) 47 7:0 langid - msb 9 string language id - msb of wlangid 48 7:0 langid - lsb 4 string language id - msb of wlangid 49 7:0 blength: manufacturer (x) 54 manufacture r string length (?blength: langid + blength: manufacturer + blength: product + blength: serial number? should be less than or equal to 152 bytes). x 66. 50 7:0 desctype 3 string descriptor type (constant value) 51 7:0 bstring: manufacturer ?2?, 0, ?0?, 0, ?1?, 0, ?4?, 0, ? ?, 0, ?c?, 0, ?y?, 0, ?p?, 0, ?r?, 0, ?e?, 0, ?s?, 0, ?s?, 0, ? ?, 0, ?s?, 0, ?e?, 0, ?m?, 0, ?i?, 0, ?c?, 0, ?o?, 0, ?n?, 0, ?d?, 0, ?u?, 0, ?c?, 0, ?t?, 0, ?o?, 0, ?r?, 0 manufacturer string: unicode utf-16le per usb 2.0 specifi- cation : ?2014 cypress semiconductor? 49 + x 7:0 blength: product (y) 22 product string lengt h (?blength: langid + bl ength: manufacturer + blength: product + blength: serial number? should be less than or equal to 152 bytes). y 66. 50 + x 7:0 desctype 3 string descriptor type (constant value) table 6. eeprom map (continued) i 2 c offset bits name default description free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 24 of 33 emi hx3 meets the emi requirements outlined by fcc 15b (usa) and en55022 (europe) for consumer electronics. hx3 tolerates emi conducted by aggressors outlined by the above specifica- tions and continues to function as expected. esd hx3 has a built-in esd protection on all pins. the esd protection level provided on these ports is 2.2 kv human body model (hbm) based on the jesd22-a114 specification. 51 + x 7:0 bstring: product ?c?, 0, ?y?, 0, ?-?, 0, ?h?, 0, ?x?, 0, ?3?, 0, ? ?, 0, ?h?, 0, ?u?, 0, ?b?, 0 product string: unicode utf-16le per usb 2.0 specification: ?cy-hx3 hub? 49 + x + y 7:0 blength: serial number (z) 22 serial numbe r string length (?blength : langid + blength: manufac- turer + blength: product + blength: serial number? should be less than or equal to 152 bytes). z 66. 50 + x + y 7:0 desctype 3 string descriptor type (constant value) 51 + x + y 7:0 bstring: serial number ?1?, 0, ?2?, 0, ?3?, 0, ?4?, 0, ?5?, 0, ?6?, 0, ?7?, 0, ?8?, 0, ?9?, 0, ?a?, 0 serial number string: unicode utf-16le per usb 2.0 specifi- cation: ?123456789a? table 6. eeprom map (continued) i 2 c offset bits name default description free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 25 of 33 absolute maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature................................... ?65 c to +150 c operating temperature .............................. ?40 c to +85 c electrostatic discharge voltage ................................. 2200 v oscillator or crystal frequency ................. 26 mhz 150 ppm i/o voltage supply ...............................................3 v to 3.6 v maximum input sink current per i/o .............................. 4 ma electrical specifications hx3 meets all usb-if electrical compliance specifications. dc electrical characteristics table 7. dc electrical characteristics parameter description conditions min typ max units dvdd12 1.2 v core supply 1.14 1.2 1.26 v vdd_efuse efuse supply normal operation 1.14 1.2 1.26 v programming 2.5 2.6 2.7 avdd12 1.2 v analog supply 1.14 1.2 1.26 v vdd_io 3.3 v i/o supply 3 3.3 3.6 v avdd33 3.3 v analog supply 3 3.3 3.6 v v ih input high voltage 0.7 vdd_io ? vdd_io v v il input low voltage 0 ? 0.3 vdd_io v v oh output high voltage output high voltage at i oh ? +4 ma 2.4 ? ? v v ol output low voltage output low voltage at i ol ? ? ?4 ma ? ? 0.4 v i os input sink current led gpio usage ? ? 4 ma i ix input leakage current all i/o signals held at vdd_io or gnd ?1 ? 1 a i oz output hi-z leakage current ? ? 10 a i cc 1.2 v supplies combined operating current ? 410 526 ma i cc 3.3 v supplies combined operating current ? 260 286 ma i sb1 total 1.2-v supply current during hx3 suspend us port is not connected ? 12 20 ma i sb2 total 3.3-v supply current during hx3 suspend us port is not connected ? 4 6 ma v ramp voltage ramp rate on core and i/o supplies voltage ramp must be monotonic 0.2 ? 50 v/ms v n noise level permitted on core and i/o supplies max p-p noise level permitted on all supplies except avdd ? ? 100 mv v n_usb noise level permitted on avdd12 and avdd33 supply max p-p noise level permitted usb supply ? ?20mv free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 26 of 33 power consumption ta b l e 8 provides the power consumption estimates for hx3 under different conditions. ta b l e 9 summarizes the power consumption for various combinations of devices connected to ds ports. for example, to calculate the hx3 power consumption for three ss devices connected to ds ports (and no device connected to one ds port), and a us port co nnected to a usb 3.0 host: power consumption = [a] + 2*[g] = 492.5 + 2*76 = 644 mw [a] is the active power consumption for the us port connected to a usb 3.0 host and the ss device connected to the ds port. [g] is the incremental power consumption for an additional ss device connected to the ds port. table 8. power consumption estimates for various usage scenarios device condition number and speed of ds ports connected typical consumption comments supply current (ma) power (mw) 1.2 v 3.3 v host not attached ? 18.0 6.0 41.4 ? suspend with host attached [13] no devices connected 42.0 12.0 90.0 ? active power with usb 3.0 host [14] 1 ss 204.1 75.0 492.5 [a] 1 hs 51.2 45.2 210.7 [b] 1 fs 51.2 34.0 173.7 [c] 1 ss + 1 hs 218.0 103.4 602.9 [d] active power with usb 2.0 host [14, 15] 1 hs 51.2 45.2 210.7 [e] 1 fs 51.2 34.0 173.7 [f] incremental active power for additional ds port ss 39.4 8.7 76.0 [g] hs 7.0 19.8 73.7 [h] fs 7.0 14.2 55.2 [i] active power saving per disabled ds port [16] ? 10.6 9.6 44.4 [j] table 9. power consumption under various configurations configuration number of ds devices connected with data transfer typical consumption comments supply current (ma) power (mw) 1.2 v 3.3 v usb 3.0 4-port hub (usb 3.0 host) 4 ss devices 322 101 720 [a] + 3*[g] 3 ss + 1 hs devices 297 121 755 [d] + 2*[g] 3 ss devices 283 92 644 [a] + 2*[g] usb 3.0 4-port hub with one port disabled (usb 3.0 host) 3 ss devices 272 83 600 [a] + 2*[g] - [j] 2 ss + 1 hs devices 247 103 634 [d] + [g] - [j] shared link with eight ds ports 4 ss + 4 hs devices 357 189 1052 [d] + 3*([g] + [h]) usb 2.0 4-port hub (usb 2.0 host) 4 hs devices 72 105 432 [e] + 3*[h] 3 hs + 1 fs devices 72 99 413 [e] + 2*[h] + [i] notes 13. us port in low-power state (ss in u3 and usb 2.0 in l2). 14. all four ds ports are enabled. 15. us ss disabled using configuration options. refer to table 6 for i 2 c configuration options. 16. power saving applicable only with a usb 3.0 host. ds ports can be disabled through configuration options. refer to table 5 for pin-strapping and table 6 for i 2 c configuration options. free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 27 of 33 ordering information ta b l e 1 0 lists hx3?s ordering information. the table contains only the part numbers that are currently available for order. additional part numbers for industrial temperature range can be made av ailable on request. for more information, visit the cypress website or contact the local sales representative. ordering code definitions table 10. ordering information ordering part number number of ds ports number of shared link ports ghost charge aca- dock tempera- ture package cyusb3302-68ltxc 2 (usb 3.0) 0 yes no 0-70 c 68-qfn cyusb3304-68ltxc 4 (usb 3.0) 0 yes no 0-70 c 68-qfn cyusb3304-68ltxi 4 (usb 3.0) 0 yes no ?40-85 c 68-qfn cyusb3312-88ltxc 2 (usb 3.0) 0 yes no 0-70 c 88-qfn cyusb3314-88ltxc 4 (usb 3.0) 0 yes no 0-70 c 88-qfn cyusb3314-88ltxi 4 (usb 3.0) 0 yes no ?40-85 c 88-qfn CYUSB3326-88ltxc 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no 0-70 c 88-qfn CYUSB3326-88ltxi 6 (2 usb 3.0, 2 ss, 2 usb 2.0) 2 yes no ?40-85 c 88-qfn cyusb3328-88ltxc 8 (4 ss, 4 usb 2.0) 4 yes yes 0-70 c 88-qfn usb cy x x - xx lt x x 3 3 temperature range: c= commercial; i= industrial pb-free package type: qfn pin count number of ports feature list: 0 = basic, 1 = advanced, 2 = shared link hub family usb 3.0 marketing code: usb company id: cy = cypress free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 28 of 33 package diagrams figure 14. 68-pin qfn (8 8 1.0 mm) lt68b 5.1 5.1 mm epad (sawn) package outline figure 15. 88-pin qfn (10 10 1.0 mm) lt88b 5.3 5.3 epad (sawn) package outline 1. hatch area is solderable exposed pad 2. reference jedec#: mo-220 3. all dimensions are in millimeters notes: 001-78925 *b 1. hatch area is solderable exposed pad 2. reference jedec#: mo-220 3. all dimensions are in millimeters notes: 001-76569 *a free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 29 of 33 acronyms reference documents usb 2.0 specification usb 3.0 specification battery charging specification document conventions units of measure table 11. acronyms used in this document acronym description aca accessory charging adapter assp application-specific standard product bc battery charging cdp charging downstream port ds downstream dcp dedicated charging port dwg device working group eeprom electrically erasable programmable read-only memory fs full-speed fw firmware gnd ground gpio general-purpose input/output hs hi-speed isp in-system programming i/o input/output ls low-speed nc no connect otg on-the-go pid product id por power-on reset rom read-only memory scl serial clock sda serial data ss superspeed tt transaction translator us upstream vid vendor id table 12. units of measure symbol unit of measure c degree celsius ? ohm gbps gigabit per second kb kilobyte khz kilohertz k ? kiloohm mbps megabit per second mhz megahertz a microampere ma milliampere ms millisecond mw milliwatt ns nanosecond ppm parts per million vvolt free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 30 of 33 errata this section describes the errata for the hx3 usb 3.0 hub. this errata is applicable to all part numbers. hx3 usb 3.0 hub qualification status product status: production with rev. *a silicon hx3 usb 3.0 hub errata summary this table defines the errata applicable to the available hx3 usb 3.0 hub devices. 1. hx3 with internal rom firmware does not pass usb- if compliance certification with rev. *a silicon. problem definition hx3 does not pass usb-if certificat ion with internal rom firmware. parameters affected n/a trigger condition(s) n/a scope of impact customer must use cypress-provided firmware available from www.cypress.com/hx3 to pass usb-if certification. workaround to pass usb-if certification, it requires cypress- provided firmware be downloaded to hx3 using (a) i 2 c eeprom or (b) external i 2 c master. a. when using i 2 c eeprom i. connect eeprom to hx3 using the i 2 c interface. ii. connect pins mode_sel[0] to high and mode_sel[1] to low respectively. refer to ta b l e 2 , table 3 , and table 4 for details on the hx3 pinout and mode selection. iii. use cypress-provided blaster plus soft ware tool to program the firmware into eepr om. the blaster plus tool, user guide, and cypress-provided firmware are available at www.cypress.com/hx3 . iv. reset or power cycle to boot hx3 with the new firmware. b. when using external i 2 c master i. connect i 2 c master to hx3 using the i 2 c interface. ii. connect pins mode_sel[0] to low and mode _sel[1] to high respectively. refer to ta b l e 2 , table 3 , and table 4 for details on the hx3 pinout and mode selection. iii. download firmware for hx3 using the external i 2 c master. iv. reset or power cycle to boot hx3 with the new firmware. the rev. *b silicon will have new internal rom firmware to pass usb-if compliance. this silicon will be drop-in compatible for all part numbers. customers could switch to the rev. *b silicon and save bom by elimi nating the eeprom. to move from rev. *a to rev. *b silicon, the following changes on the pcb are recommended: i. connect pins mode_sel[0] and mode_sel[1] to high. ii. eeprom need not be popul ated unless required for custom configurations. iii. during pcb design, make provision for mode_sel[1:0] pins to be configured as high or low. fix status to be fixed in the rev. *b silicon and will be available by july 1, 2014. no. items part number fix status 1 hx3 with internal rom firmware does not pass usb-if compliance certification with rev. *a silicon. all to be fixed in rev. *b silicon 2 the hx3 us port should not be connected to an fs-only hub or host. all to be fixed in rev. *b silicon free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 31 of 33 2. the hx3 us port should not be connected to an fs-only hub or host. problem definition if an hx3 us port is connected to a fs hub or host, fs devices connected to the ds ports ma y not enumerate. the hx3 us port connected to an hs/ss host or hub will not have this problem. parameters affected n/a trigger condition(s) n/a scope of impact the hx3 us port should not be connected to an fs-only hub or host. workaround n/a fix status to be fixed in the rev. *b silicon and will be available by july 1, 2014. free datasheet http://www.0pdf.com
cyusb330x cyusb331x cyusb332x document number: 001-73643 rev. *f page 32 of 33 document history page document title: cyusb330x, cyusb3 31x, cyusb332x, hx3 usb 3.0 hub document number: 001-73643 revision ecn orig. of change submission date description of change *f 4291210 murt 02/25/2014 post to web. free datasheet http://www.0pdf.com
document number: 001-73643 rev. *f revised february 25, 2014 page 33 of 33 ghost charge? and shared link? are trademarks of cypress semiconductor corp. all other products and company names mentioned in this document may be the trademarks of their respective holders. cyusb330x cyusb331x cyusb332x ? cypress semiconductor corporation, 2011-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support free datasheet http://www.0pdf.com

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